Roberto
Rodríguez Osorio
Profesor Titular de Universidad
Publicaciones (47) Publicaciones de Roberto Rodríguez Osorio
2023
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Floating Point Calculation of the Cube Function on FPGAs
IEEE Transactions on Parallel and Distributed Systems, Vol. 34, Núm. 1, pp. 372-382
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Implementation of a motion estimation algorithm for Intel FPGAs using OpenCL
Journal of Supercomputing, Vol. 79, Núm. 9, pp. 9866-9888
2022
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An efficient ant colony optimization framework for HPC environments
Applied Soft Computing, Vol. 114
2020
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Comparison of hardwired and microprogrammed statechart implementations
Electronics (Switzerland), Vol. 9, Núm. 7, pp. 1-18
2019
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A Microprogrammed Approach for Implementing Statecharts
Proceedings - Euromicro Conference on Digital System Design, DSD 2019
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Hardware Implementation of Statecharts for FPGA-based Control in Scientific Facilities
2019 34th Conference on Design of Circuits and Integrated Systems, DCIS 2019
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Truncated SIMD multiplier architecture for approximate computing in low-power programmable processors
IEEE Access, Vol. 7, pp. 56353-56366
2017
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Timing system at ESS
IPAC 2017 - Proceedings of the 8th International Particle Accelerator Conference
2016
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A fast algorithm for constructing nearly optimal prefix codes
Software - Practice and Experience, Vol. 46, Núm. 10, pp. 1299-1316
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Modular architecture for multiple transforms in modern video standards
2016 Conference on Design of Circuits and Integrated Systems, DCIS 2016 - Proceedings
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Pipelined FPGA implementation of numerical integration of the Hodgkin-Huxley model
Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
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Transaction level and RTL modeling of an architecture for network data compression within ethernet switches in large file transfer scenarios
2016 Conference on Design of Circuits and Integrated Systems, DCIS 2016 - Proceedings
2013
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Architecture and implementation of a data compression system at switch-level in ATA-over-ethernet storage networks
Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013
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High-speed FPGA architecture for CABAC decoding acceleration in H.264/AVC standard
Journal of Signal Processing Systems, Vol. 72, Núm. 2, pp. 119-132
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Improving scalability of application-level checkpoint-recovery by reducing checkpoint sizes
New Generation Computing
2012
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Fast construction of nearly-optimal prefix codes without probability sorting
Data Compression Conference Proceedings
2009
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A digital cellular-based system for retinal vessel-tree extraction
ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program
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High performance image processing on a massively parallel processor array
12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009
2008
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An FPGA architecture for CABAC decoding in manycore systems
Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
2007
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Entropy coding on a programmable processor array for multimedia SoC
2007 IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES, AND PROCESSORS