Roberto
Rodríguez Osorio
Profesor Titular de Universidad
Universidade de Santiago de Compostela
Santiago de Compostela, EspañaPublicaciones en colaboración con investigadores/as de Universidade de Santiago de Compostela (21)
2023
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Implementation of a motion estimation algorithm for Intel FPGAs using OpenCL
Journal of Supercomputing, Vol. 79, Núm. 9, pp. 9866-9888
2013
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High-speed FPGA architecture for CABAC decoding acceleration in H.264/AVC standard
Journal of Signal Processing Systems, Vol. 72, Núm. 2, pp. 119-132
2009
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A digital cellular-based system for retinal vessel-tree extraction
ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program
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High performance image processing on a massively parallel processor array
12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009
2008
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An FPGA architecture for CABAC decoding in manycore systems
Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
2007
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Entropy coding on a programmable processor array for multimedia SoC
2007 IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES, AND PROCESSORS
2006
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A Unified Architecture for H.264 multiple block-size DCT with fast and low cost quantization
DSD 2006: 9TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS
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A combined memory compression and hierarchical motion estimation architecture for video encoding in embedded systems
Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006
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A combined memory compression and hierarchical motion estimation architecture for video encoding in embedded systems
DSD 2006: 9TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS
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A unified architecture for H.264 multiple block-size DCT with fast and low cost quantization
Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006
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High-throughput architecture for H.264/AVC CABAC compression system
IEEE Transactions on Circuits and Systems for Video Technology, Vol. 16, Núm. 11, pp. 1376-1384
2005
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A new architecture for fast arithmetic coding in H.264 Advanced Video Coder
DSD 2005: 8TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, PROCEEDINGS
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A new architecture for fast arithmetic coding in H.264 advanced video coder
Proceedings - DSD'2005: 8th Euromicro Conference on Digital System Design - Architectures, Methods and Tools
2004
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Arithmetic coding architecture for H.264/AVC CABAC compression system
Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004
2000
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Architectures for arithmetic coding in image compression
European Signal Processing Conference
1999
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New model for arithmetic coding/decoding of multilevel images based on a cache memory
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
1998
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Arithmetic image coding/decoding architecture based on a cache memory
Proceedings - 24th EUROMICRO Conference, EURMIC 1998
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Arithmetic image coding/decoding architecture based on a cache memory
24TH EUROMICRO CONFERENCE - PROCEEDING, VOLS 1 AND 2
1997
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New arithmetic coder/decoder architectures based on pipelining
Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
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VLSI implementation of an arithmetic coder for image compression
Proceedings of the EUROMICRO Conference