Publicacións en colaboración con investigadores/as de Universidade de Santiago de Compostela (21)

2023

  1. Implementation of a motion estimation algorithm for Intel FPGAs using OpenCL

    Journal of Supercomputing, Vol. 79, Núm. 9, pp. 9866-9888

2013

  1. High-speed FPGA architecture for CABAC decoding acceleration in H.264/AVC standard

    Journal of Signal Processing Systems, Vol. 72, Núm. 2, pp. 119-132

2009

  1. A digital cellular-based system for retinal vessel-tree extraction

    ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program

  2. High performance image processing on a massively parallel processor array

    12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009

2008

  1. An FPGA architecture for CABAC decoding in manycore systems

    Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

2007

  1. Entropy coding on a programmable processor array for multimedia SoC

    2007 IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES, AND PROCESSORS

2006

  1. A Unified Architecture for H.264 multiple block-size DCT with fast and low cost quantization

    DSD 2006: 9TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS

  2. A combined memory compression and hierarchical motion estimation architecture for video encoding in embedded systems

    DSD 2006: 9TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS

  3. A combined memory compression and hierarchical motion estimation architecture for video encoding in embedded systems

    Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006

  4. A unified architecture for H.264 multiple block-size DCT with fast and low cost quantization

    Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006

  5. High-throughput architecture for H.264/AVC CABAC compression system

    IEEE Transactions on Circuits and Systems for Video Technology, Vol. 16, Núm. 11, pp. 1376-1384

2005

  1. A new architecture for fast arithmetic coding in H.264 Advanced Video Coder

    DSD 2005: 8TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, PROCEEDINGS

  2. A new architecture for fast arithmetic coding in H.264 advanced video coder

    Proceedings - DSD'2005: 8th Euromicro Conference on Digital System Design - Architectures, Methods and Tools

2004

  1. Arithmetic coding architecture for H.264/AVC CABAC compression system

    Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004

2000

  1. Architectures for arithmetic coding in image compression

    European Signal Processing Conference

1999

  1. New model for arithmetic coding/decoding of multilevel images based on a cache memory

    Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

1998

  1. Arithmetic image coding/decoding architecture based on a cache memory

    24TH EUROMICRO CONFERENCE - PROCEEDING, VOLS 1 AND 2

  2. Arithmetic image coding/decoding architecture based on a cache memory

    Proceedings - 24th EUROMICRO Conference, EURMIC 1998

1997

  1. New arithmetic coder/decoder architectures based on pipelining

    Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

  2. VLSI implementation of an arithmetic coder for image compression

    Proceedings of the EUROMICRO Conference