Publicaciones (38) Publicaciones de Gabriel Rodríguez Álvarez

2024

  1. Formal Verification of Source-to-Source Transformations for HLS

    FPGA 2024 - Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

2022

  1. Custom High-Performance Vector Code Generation for Data-Specific Sparse Computations

    Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

2021

  1. Optimizing Coherence Traffic in Manycore Processors Using Closed-Form Caching/Home Agent Mappings

    IEEE Access, Vol. 9, pp. 28930-28945

  2. PolyBench/Python: Benchmarking Python environments with polyhedral optimizations

    CC 2021 - Proceedings of the 30th ACM SIGPLAN International Conference on Compiler Construction

  3. Representing integer sequences using piecewise-affine loops

    Mathematics, Vol. 9, Núm. 19

2019

  1. Affine Modeling of Program Traces

    IEEE Transactions on Computers, Vol. 68, Núm. 2, pp. 294-300

  2. Effect of distributed directories in mesh interconnects

    Proceedings - Design Automation Conference

  3. Generating piecewise-regular code from irregular structures

    Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)

  4. Simulating the Network Activity of Modern Manycores

    IEEE Access, Vol. 7, pp. 81195-81210

  5. Truncated SIMD multiplier architecture for approximate computing in low-power programmable processors

    IEEE Access, Vol. 7, pp. 56353-56366

2017

  1. An application-level solution for the dynamic reconfiguration of mpi applications

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2016

  1. Locality-Aware Automatic Parallelization for GPGPU with OpenHMPP Directives

    International Journal of Parallel Programming, Vol. 44, Núm. 3, pp. 620-643

  2. Portable application-level checkpointing for hybrid MPI-OpenMP applications

    Procedia Computer Science

  3. Trace-based affine reconstruction of codes

    Proceedings of the 14th International Symposium on Code Generation and Optimization, CGO 2016

2015

  1. I/O optimization in the checkpointing of OpenMP parallel applications

    Proceedings - 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015

2014

  1. A parallelizing compiler for multicore systems

    Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2014

  2. Extending an application-level checkpointing tool to provide fault tolerance support to openMP applications

    Journal of Universal Computer Science, Vol. 20, Núm. 9, pp. 1352-1372

  3. Failure avoidance in MPI applications using an application-level approach

    Computer Journal, Vol. 57, Núm. 1, pp. 100-114

  4. In-memory application-level checkpoint-based migration for MPI programs

    Journal of Supercomputing, Vol. 70, Núm. 2, pp. 660-670

  5. Volatile STT-RAM scratchpad design and data allocation for low energy

    ACM Transactions on Architecture and Code Optimization, Vol. 11, Núm. 4