Publicaciones en las que colabora con Diego Andrade Canosa (23)

2020

  1. An automatic optimizer for heterogeneous devices

    Future Generation Computer Systems, Vol. 106, pp. 572-584

2019

  1. A Fast Solver for Large Tridiagonal Systems on Multi-Core Processors (Lass Library)

    IEEE Access, Vol. 7, pp. 23365-23378

2018

  1. Guiding the Optimization of Parallel Codes on Multicores Using an Analytical Cache Model

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  2. Heterogeneous distributed computing based on high-level abstractions

    Concurrency Computation

2017

  1. Facilitating the development of stencil applications using the Heterogeneous Programming Library

    Concurrency Computation , Vol. 29, Núm. 12

  2. High productivity multi-device exploitation with the Heterogeneous Programming Library

    Journal of Parallel and Distributed Computing, Vol. 101, pp. 51-68

2016

  1. Towards a High Level Approach for the Programming of Heterogeneous Clusters

    Proceedings of the International Conference on Parallel Processing Workshops

2015

  1. Developing adaptive multi-device applications with the Heterogeneous Programming Library

    Journal of Supercomputing, Vol. 71, Núm. 6, pp. 2204-2220

2014

  1. A fine-grained thread-aware management policy for shared caches

    Concurrency Computation Practice and Experience

  2. Address independent estimation of the boundaries of cache performance

    Microprocessors and Microsystems, Vol. 38, Núm. 2, pp. 137-151

  3. Automatic Generation of Optimized OpenCL Codes Using OCLoptimizer

    Computer Journal, Vol. 58, Núm. 11, pp. 3057-3073

  4. Writing self-adaptive codes for heterogeneous systems

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2013

  1. Accurate prediction of the behavior of multithreaded applications in shared caches

    Parallel Computing, Vol. 39, Núm. 1, pp. 36-57

2012

  1. Static analysis of the worst-case memory performance for irregular codes with indirections

    Transactions on Architecture and Code Optimization, Vol. 9, Núm. 3

  2. Using an analytical model of shared caches for selecting the optimal parallelization scheme

    Proceedings of the 2012 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2012

2010

  1. Address-independent estimation of the worst-case memory performance

    IEEE Transactions on Industrial Informatics, Vol. 6, Núm. 4, pp. 664-677

2009

  1. Static prediction of worst-case data cache performance in the absence of base address information

    Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS

2007

  1. Automated and accurate cache behavior analysis for codes with irregular access patterns

    Concurrency Computation Practice and Experience

  2. Cache behavior modelling for codes involving banded matrices

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

  3. Precise Automatable Analytical Modeling of the Cache Behavior of Codes with Indirections

    ACM Transactions on Architecture and Code Optimization, Vol. 4, Núm. 3, pp. 16