Ramón
Doallo Biempica
Catedrático de Universidade
Emilio
López Zapata
Publicacións nas que colabora con Emilio López Zapata (23)
2004
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A compiler tool to predict memory hierarchy performance of scientific codes
Parallel Computing, Vol. 30, Núm. 2, pp. 225-248
2003
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Probabilistic miss equations: Evaluating memory hierarchy performance
IEEE Transactions on Computers, Vol. 52, Núm. 3, pp. 321-336
1999
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Automatic analytical modeling for the estimation of cache misses
Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT, pp. 221-231
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Direct mapped cache performance modeling for sparse matrix operations
Proceedings of the 7th Euromicro Workshop on Parallel and Distributed Processing, PDP 1999
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HPF-2 support for dynamic sparse computations
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
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Set associative cache behavior optimization
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
1998
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Cache misses prediction for high performance sparse algorithms
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
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Cache probabilistic modeling for basic sparse algebra kernels involving matrices with a non-uniform distribution
Proceedings - 24th EUROMICRO Conference, EURMIC 1998
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Modeling set associative caches behavior for irregular computations
Performance Evaluation Review, Vol. 26, Núm. 1, pp. 192-201
1997
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High-performance VLSI architecture for the viterbi algorithm
IEEE Transactions on Communications, Vol. 45, Núm. 2, pp. 168-176
1996
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Parallel sparse modified gram-schmidt QR decomposition
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
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Sparse Householder QR factorization on a mesh
Proceedings of 4th Euromicro Workshop on Parallel and Distributed Processing, PDP 1996
1991
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Design of a constant geometry fast Hartley transformer
Proceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing
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Diseño de un procesador para la identificación de patrones
Diseño de circuitos integrados: actas del VI Congreso. Santander, 11/15 de noviembre de 1991
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Semisystolic architecture for fast Hartley transform. Decimation in frequency and radix 2
IEE Proceedings, Part G: Circuits, Devices and Systems, Vol. 138, Núm. 6, pp. 651-660
1990
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A VLSI systolic architecture for solving DBT-transformed fuzzy clustering problems of arbitrary size
Parallel Computing, Vol. 13, Núm. 3, pp. 321-335
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ACLE. A software package for SIMD computer simulation
Computer Journal, Vol. 33, Núm. 3, pp. 194-203
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Gaussian elimination with pivoting on hypercubes
Parallel Computing, Vol. 14, Núm. 1, pp. 51-60
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Software tools for multiprocessor simulation and programming
Cybernetics and Systems, Vol. 21, Núm. 2-3, pp. 291-310
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Systolic architecture for the calculation of the correlation coefficients
Microprocessing and Microprogramming, Vol. 30, Núm. 1-5, pp. 609-616