200 Mbit/s 4-symbol arithmetic encoder architecture for embedded zero tree-based compression

  1. Osorio, RR
  2. Vanhoof, B
Book:
SIPS 2001: IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: DESIGN AND IMPLEMENTATION
  1. Catthoor, F (coord.)
  2. Moonen, M (coord.)

ISBN: 0-7803-7145-3

Year of publication: 2001

Pages: 397-405

Congress: IEEE Workshop on Signal Processing, Systems Design and Implementation (SiPS 01)

Type: Conference paper

DOI: 10.1109/SIPS.2001.957367 GOOGLE SCHOLAR
Data source: WoS